A System-On-a-Chip (SoC) system is an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate. The term “package” refers to the material added around a component or integrated circuit (SoC) to allow it to be handled without damage and incorporated into a circuit. A ball grid array (BGA) package is a type of surface-mount packaging used for integrated circuits. The “die” refers to the IC chip itself and a “bond pad” refers to a soldering location on the die for connecting a lead finger of a BGA package to the die using a bond wire. The term “ballmap” refers to the mapping of bond pads to the lead fingers of the BGA package. The ballmap also typically includes mapping for signal and power (VDD/VSS). A ballmap drawing usually includes at least a die, a package, and the mapping connecting the appropriate bond pads to the lead fingers of BGA package. System in Package (SiP) designs generally refer to the integration of multiple IC chips into a larger package to create a large scale system located on a common printed circuit board (PCB).
The semiconductor industry is under increasing pressure to reduce power requirements, down-size devices, leverage advanced technology, and create multi-function devices. The industry-wide roadmap for integrated circuit design has been to reduce size, reduce power supply voltage, reduce cost and increase circuit density. Semiconductor packaging must keep pace to support these continually changing design objectives. BGA package offers cost effective option compared to other package technologies like Flip Chip, however bond wires, specially long bond wires, in BGA packages gives higher inductance, this makes system susceptible to noise. With continual reductions in operating voltages to meet lower power requirements, noise margins have also decreased, leaving the devices increasingly susceptible to electrical noise. Noise suppression therefore becomes more challenging with advancements in integrated circuit capabilities, potentially presenting a limiting factor for certain design advancements.
Ground bounce and switching ground noise at the power supplies for high switching rate devices, such as memory clock signals, can be primary sources of electrical noise. Noise generation and the sensitivity of the circuits to noise tend to increase as the memory clock signal rate increases. Reducing electrical noise in general, and reducing power supply ground bounce and switching ground noise in particular, are therefore increasingly important design objectives to support decreasing operating voltages and increased memory and other circuit clock rates.
There is, therefore, a continuing need for improved integrated circuit design techniques for reducing size, reducing power supply voltage, increasing circuit clock rates, and increasing circuit density. More particularly, there is a continuing need for reducing power supply ground bounce and switching ground noise in order to accommodate reduced noise margins, reduced power supply voltages, and increased memory clock rates.